Complementary metal oxide semiconductor (CMOS) devices comprising interconnected P-channel and N-channel metal oxide semiconductor (MOS) transistors are commonly used in the semiconductor art. In typical thin film silicon-on-insulator (SOI) MOS devices, an anomalous leakage path is formed along the bottom of the transistor(s) of the device, from source to drain. The leakage path or paths may be caused by charge buildup in the insulator under the transistor(s) after a burst of ionizing radiation, or may be present in the insulator(s) during the formation of the device(s). A substrate bias can be used to turn off the leakage path in one transistor type (N or P). However, in CMOS/SOI circuits, the substrate bias that turns off one device causes the other device of opposite conductivity to turn on.
Current leakage or the reduction of current leakage paths is typically an on-going concern for designers of various semiconductor devices. For example, in Japanese Patent No. 61-232676(A), issued on Oct. 16, 1986, and entitled "Semiconductor Device", a CMOS device is disclosed. The device consists of an N- silicon substrate 1, including thereon juxtaposed N and P-channel devices. A PN junction is formed longitudinally in the semiconductor substrate below an insulating layer 2 of SIO.sub.2, with the P-channel and N-channel devices being located on top of the insulating layer. The PN junction is formed from a P+ region 11 directly under the central N region 3'C of the PMOS device 3' in the N- substrate 11 below the dielectric layer 2. It is indicated that the PN junction prevents a back channel from being formed "in a device of an SOI structure." It is further indicated that "in this structure, when a positive surge voltage is applied to the substrate 1, a depletion layer is extended, and it is absorbed."
The present inventors believe that the device illustrated in the subject Japanese Patent, uses the P+ region 11 in an AC-like mode, wherein during transient or pulse-like conditions, when a positive pulse or transient surge of voltage is applied to the substrate 1, the P+ region 11 acts in some manner to prevent leakage current from flowing, but the mechanism for preventing such leakage current is unclear. Also, it appears that the P+region 11 must be separated from the source region 3'S and drain region 3'D to prevent capacitive coupling between these regions and the P+ region 11. It is believed that such coupling would disturb the operation of the CMOS device under typical pulse conditions. For proper operation, the oxide capacitance of layer 2 must be substantially larger than the PN junction depletion capacitance between layers 1 and 11.
Gutknecht 4,065,781 discloses an insulated gate thin film transistor including a first or channel semiconductor layer, and a second semiconductor layer contacting the first layer, and also the source electrode of the transistor. This contact is made at least between the source and drain electrodes of the first semiconductor layer. The second semiconductor layer is opposite in conductivity type to the first or channel semiconductor layer, and forms a PN heterojunction with the latter.
Goodman et al. 4,091,527 teaches a method of annealing a silicon substrate in a reducing atmosphere, for preoxidizing the silicon, in order to reduce the leakage current of an N channel transistor to be formed on the substrate subsequent to the annealing process.
MacPherson et al. 4,309,715 teaches the use of a shield region in a solid-state structure for a high voltage switch. The shield region is biased to decrease the turn-on time of the switch.
Benyon et al. 4,313,809 teaches the step of subjecting a completed SOS device to a sputtering operation for depositing a metalized layer on the device, which layer is subsequently removed prior to scribing and dicing. In this manner edge current leakage is reduced.
Ohno 4,507,846 discloses a method for producing silicon-on-sapphire (SOS) semiconductors for providing a CMOS device or devices. A portion of the semiconductor layer between the gate electrodes of the N channel and P-channel devices is removed, whereafter N type and P type impurities are doped into the N-channel and P-channel transistors, respectively, using the gate electrodes as a mask, in order to reduce leakage current.